1. Field of Invention
The present invention relates to a method of forming the multi-level interconnects of semiconductor devices. More particularly, the present invention relates to a method of forming a dual damascene structure.
2. Description of Related Art
In semiconductor fabrication, various devices are interconnected by conductive lines. In general, the connection point between a conductive wire and an integrated circuit device is referred to as a contact and the connection point between conductive wires is referred to as a via. Resistance along a piece of the conductive wire and parasitic capacitance between conductive wires are major factors that are likely to affect the operating speed of a semiconductor device. In the fabrication of a deep sub-micron semiconductor device, copper is gradually replacing aluminum as the material for forming conductive wires. In the meantime, a low dielectric constant (low K) material is often employed to fabricate inter-metal dielectric layers. Ultimately, resistance-capacitance (RC) delay of the conductive wire is reduced while anti-electromigration capacity of the conductive wire is increased. This is because the capacity to resist electromigration in copper is some 30 to 100 times that of aluminum, via resistance is lowered 10 to 20 times and resistance value is lowered by 30%. However, copper is difficult to etch. Hence, a damascene process is normally employed to fabricate copper interconnects instead of a conventional patterning method.
In general, dual damascene processes can be divided into self-aligned dual damascene (SADD) processes, trench first dual damascene (TFDD) processes and via-first dual damascene (VFDD) processes. FIGS. 1A through 1E are schematic cross-sectional views showing the progression of steps for fabricating a conventional via-first dual damascene structure. First as shown in FIG. 1A, a substrate 100 having a conductive line 102 therein is provided. A passivation layer 104, a first dielectric layer 106, an etching stop layer 108, a second dielectric layer 110, a cap layer 112 and a base anti-reflection coating 114 are sequentially formed over the substrate 100. A positive photoresist layer 116 is formed over the base anti-reflection coating 114. Photolithographic and etching processes of the positive photoresist layer 116 are conducted to form an opening 117. Using the positive photoresist layer 116 as a mask, a portion of the base anti-reflection coating 114, the cap layer 112, the dielectric layer 110, the etching stop layer 108 and the dielectric layer 106 are sequentially removed to form a via opening 118. The via opening 118 exposes a portion of the passivation layer 104.
As shown in FIG. 1B, the positive photoresist layer 116 and the base anti-reflection coating 114 are removed. Thereafter, a trench-filling material 120 is deposited over the substrate 100, completely filling the via opening 118. A back-etching operation is conducted to remove excess trench-filling material 120 outside the via opening 118. Another base anti-reflection layer 122 and another positive photoresist layer 124 are sequentially formed over the substrate 100. The positive photoresist layer 124 is patterned to form an opening 125 by conducting photolithographic and etching processes.
As shown in FIG. 1C, using the positive photoresist layer 124 as a mask, a portion of the base anti-reflection layer 122, the cap layer 112 and the dielectric layer 110 is removed to form a trench 126. In the meantime, a portion of the trench-filling material 120 is also removed. Afterwards, both the positive photoresist layer 124 and the low anti-reflection layer 122 are removed.
As shown in FIG. 1D, the trench-filling material 120 is removed. In a subsequent step, a portion of the etching stop layer 108 exposed by the opening 126 and a portion of the passivation layer 104 exposed by the via opening 118 are removed. Hence, the conductive line 102 in the substrate 100 is exposed.
As shown in FIG. 1E, a conformal barrier layer 128 is formed over the substrate 100. A conductive layer 130 is formed over the barrier layer 128, completely filling the via opening 118 and the trench 126. A planarization operation such as a chemical-mechanical polishing is carried out so that excess conductive and barrier material outside the via opening 118 and the trench 126 are removed.
In the aforementioned via-first dual damascene process, trench-filling material 120 is deposited into the via opening 118. The trench-filling material 120 prevents the entrance of any residual positive photoresist material 124 into the via opening 118, whereby the via plug resistance and RC delay would be increased. However, as line width reduces to 0.13 xcexcm or less, trench-filling material cannot fill an opening having an aspect ratio greater than 5. Furthermore, residual trench-filling material may be retained in the corner regions of the via opening 118 and the trench 126, thereby forming what are known as fence structures 132 around the via opening 118. When barrier material 128 is deposited into the opening 118 and the trench 126, the barrier layer 128 may be broken by the fence structures, leading to a deterioration of the barrier function. This may lead to bridging between metallic interconnects or even device failure.
The base anti-reflection layer 114, the cap layer 112, the dielectric layer 110, the etching stop layer 108 and the dielectric layer 106 are sequentially etched to form the via opening 118 while using the positive photoresist layer 116 as a mask. Since etching depth of two consecutive dielectric layers is considerable, a relatively thick positive photoresist layer 116 is required to pattern the via opening 118. A thick photoresist layer not only increases production cost, but also leads to a drop in production quality and possible peeling of the photoresist layer.
Furthermore, dielectric material with a low dielectric constant (below 3) such as vapor-phase deposition polymers (VPDP), spin-on dielectric (SOD) or spin-on glass (SOG) is often used in the production process. Density, hardness and mechanical strength of these materials are usually small. Hence, slight internal stress may result in large deformation of the via structures and creation of weak spots. Ultimately, production yield is affected.
Accordingly, one object of the present invention is to provide a method of forming a dual damascene structure capable of minimizing resistance-capacitance delay and increasing device performance.
A second object of this invention is to provide a method of forming a dual damascene structure capable of maintaining identical critical dimension, reducing photoresist cost and increasing process tolerance.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a dual damascene structure. A substrate having a conductive layer thereon is provided. A passivation layer, a first dielectric layer, an etching stop layer, a second dielectric layer and cap layer serving as a base anti-reflection coating are sequentially formed over the substrate. The cap layer and the second dielectric layer are patterned to form a first opening that exposes a portion of the etching stop layer. A patterned negative photoresist layer having a second opening therein is formed above the cap layer. The cap layer exposed by the second opening and the second dielectric layer exposed by the first opening are removed. Thereafter, the second dielectric layer exposed by the second opening is removed to form a trench and the first dielectric layer exposed by the first opening is removed to form a via opening. The passivation layer exposed by via opening and then the negative photoresist layer is removed. A conformal barrier layer and a conductive layer are sequentially formed over the trench and the via opening with the conductive layer, completely filling the trench and the via opening.
In addition, this invention may employ a via-first method. A first dielectric layer, a second dielectric layer and a base anti-reflection coating are sequentially formed over a substrate having a conductive layer therein. The base anti-reflection layer, the second dielectric layer and the first dielectric layer are patterned to form a via opening that exposes a portion of the conductive layer. A negative photoresist layer is formed over the base anti-reflection layer. The negative photoresist layer is patterned to form an opening. Using the patterned negative photoresist layer as a mask, the exposed anti-reflection layer and the second dielectric layer are removed to form a trench that exposes a portion of the first dielectric layer. The negative photoresist layer is subsequently removed. Finally, a conformal barrier layer and a conductive layer are sequentially formed over the trench and the via opening with the conductive layer, completely filling the trench and the via opening.
In this invention, a negative photoresist is used to pattern a trench pattern so that the unexposed negative photoresist in the trench region can be removed by chemical developer. Since no photoresist residues are formed, there is no need to deposit trench-filling material into the via opening to maintain proper resistance-capacitance delay. Because trench-filling material is not used in the fabrication process, fence structures are no longer formed in the corner regions of the via opening and the trench. Hence, abnormal bridging between metallic interconnects that may lead to device failure can be prevented.
In addition, this invention also provides a partial etching process to pattern composite low dielectric constant material. Moreover, negative photoresist, which has a higher etching resistance than conventional positive photoresist, is used to form the etching mask. Hence, overall thickness of the negative photoresist layer can be reduced and uniformity of critical dimension is improved. Ultimately, less photoresist material is required and process tolerance is increased. The selection of a low dielectric constant material with a higher density to form the dielectric layer of the dual damascene structure also prevent structural deformation around the via region.
Furthermore, the cap layer for patterning the via opening and the trench is directly used as an anti-reflection layer. Since there is no need to form an anti-reflection layer over the cap layer, some production cost is saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.